1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory including a memory cell array which includes a plurality of electrically rewritable memory cells, and a data reading method.
2. Description of the Related Art
Recently, a demand for compact and large-capacity nonvolatile semiconductor memories has been rapidly increased. Among them, a NAND type flash memory expected to be integrated to a higher degree and to have a larger capacity than a conventional NOR type flash memory has been a center of attention. A NAND type flash memory includes a plurality of memory cells, having a floating gate, which are connected in series, and can act as a memory by programming data to, or reading data from, each of the memory cells.
The NAND type flash memory, however, has a problem that along the recent increase in the integration degree, the size of the structure has been more and more reduced, which causes a capacitance to be formed between floating gates of adjacent memory cells and thus generates noise.
One technology for suppressing the noise is a nonvolatile semiconductor memory described in, for example, Japanese Laid-Open Patent Publication No. 2004-326866. The nonvolatile semiconductor memory includes a memory cell array and a plurality of sense amplifier circuits. The memory cell array includes electrically rewritable, floating gate type memory cells. The plurality of sense amplifier circuits are provided for reading data from the memory cell array.
Each sense amplifier circuit senses cell data in a first memory cell selected from the memory cell array, under a reading condition which is determined in accordance with data in a second memory cell which is adjacent to the first memory cell and to which data is programmed after data is programmed to the first memory cell.
For example, Japanese Laid-Open Patent Publication No. 2004-192789 describes a technology, by which before data is stored on a memory cell having i-bit data stored thereon, i-bit or less amount of data is programmed to a memory cell adjacent thereto.
However, these technologies also have a problem that coupling noise needs to be suppressed more efficiently.